Command clock gate implementation with chip select signal training indication
US11823729B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Dec 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for gating, via clock gating circuitry, a clock signal based at least in part on a mode register value indicative of synchronization of a command address signal with the clock signal when the mode register value indicates synchronization of the command address signal with the clock signal has not occurred. The clock gating circuitry is configured to, gate the clock signal based at least in part on the mode register value and a chip select signal value when the mode register value indicates synchronization of the command address signal with the clock signal has occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.