3D NAND memory device and method of forming the same
US11825656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2022 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Jun 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.