Receiver circuit, memory device and operation method using the same
US11830535B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Oct 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. A first pre-stage amplifier circuit includes a pair of first n-type transistors, and gate terminals of the first pair of the n-type transistors receive the input signal and the reference voltage signal, respectively. A second pre-stage amplifier circuit includes a pair of first p-type transistors, wherein gate terminals of the pair of the first p-type transistors receive the input signal and the reference voltage signal, respectively. The post-stage amplifier circuit outputs a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals. A memory device including the receiver circuit and an operation method thereof are also introduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.