Chi Lo
12Patents
3h-index
5Co-inventors
49Inventor score
Filing activity: May 5, 2011 → Jul 25, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9690650B2 | Storage scheme for built-in ECC operations | Physics | 15 | Active |
| US9165680B2 | Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks | Physics | 6 | Active |
| US8432746B2 | Memory page buffer | Emerging Cross-Sectional Technologies | 3 | Active |
| US9773571B2 | Memory repair redundancy with array cache redundancy | Physics | 2 | Active |
| US9147485B2 | Memory page buffer | Emerging Cross-Sectional Technologies | 2 | Active |
| US11189339B1 | Performing in-memory computing based on multiply-accumulate operations using non-volatile memory arrays | Physics | 1 | Active |
| US10290364B2 | Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks | Physics | 1 | Active |
| US9478314B2 | Memory utilizing bundle-level status values and bundle status circuits | Physics | 0 | Active |
| US12106798B2 | Receiver circuit, memory device and operation method using the same | Physics | 0 | Active |
| US9570186B2 | Memory page buffer | Emerging Cross-Sectional Technologies | 0 | Active |
| US10643737B2 | Method for an integrated circuit memory with a status memory for storing repair statuses of row blocks of main column blocks | Physics | 0 | Active |
| US11830535B2 | Receiver circuit, memory device and operation method using the same | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.