Detecting bit line open circuits and short circuits in memory device with memory die bonded to control die
US11830564B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Mar 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are presented for detecting bit line open circuits and short circuits in a memory device in which a memory die is inverted and bonded to a control die. In one approach, the control die comprises a set of bit lines which are connected to a set of bit lines of the memory die, and the set of bit lines of the control die comprise ground transistors, e.g., transistors connected to a ground node. Ground transistors of even-numbered bit lines may be commonly controlled, while ground transistors of odd-numbered bit lines are commonly controlled. The ground transistors may be controlled to detect open circuits and short circuits in the bit lines of the control die and the memory die. A laser scanning technique can also be used to determine a physical location of a defect of a bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.