Back-side wafer modification
US11830778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2020 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Mar 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.