Creating interconnects between dies using a cross-over die and through-die vias

US11830817B2 · kind B2 · utility

Assignees

• Advanced Micro Devices, Inc. · US
• ATI Technologies ULC · CA

Inventors

• Rahul Agarwal · Livermore, US
• Raja Swaminathan · Santa Clara, US
• Michael Alfano · Austin, US
• Gabriel H. Loh · Bellevue, US
• Alan D. Smith · Henrietta, US
• Gabriel Wong · Honolulu, US
• Michael Mantor · Orlando, US

Key dates

• Filing date: Oct 30, 2020
• Grant date: Nov 28, 2023
• Expiry date: Oct 30, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06562
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.