Inner spacer formation in multi-gate transistors
US11830928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Jan 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02332
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.