Constraints and objectives used in synthesis of a network-on-chip (NoC)
US11836427B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Sep 19, 2022 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Sep 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.