Non-volatile memory with adjusted bit line voltage during verify
US11837296B2 · kind B2 · utility
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7References
20Claims
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Key dates
| Filing date | Oct 19, 2021 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Apr 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.