Fabricating field-effect transistors with interleaved source and drain finger configuration
US11842947B2 · kind B2 · utility
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Key dates
| Filing date | May 11, 2021 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Dec 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.