Methods for pillar connection on frontside and passive device integration on backside of die
US11842997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2022 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Mar 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.