Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells
US11844202B2 · kind B2 · utility
0Cited by
6References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2022 |
| Grant date | Dec 12, 2023 |
| Priority date | — |
| Expiry date | Nov 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.