Purnima Narayanan
19Patents
4h-index
30Co-inventors
56Inventor score
Filing activity: Nov 1, 2013 → Jun 6, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9431410B2 | Methods and apparatuses having memory cells including a monolithic semiconductor channel | Electricity | 11 | Active |
| US10777576B1 | Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies | Electricity | 9 | Active |
| US9741734B2 | Memory devices and systems having reduced bit line to drain select gate shorting and associated methods | Electricity | 5 | Active |
| US10134758B2 | Memory devices and systems having reduced bit line to drain select gate shorting and associated methods | Electricity | 4 | Active |
| US10090317B2 | Methods and apparatuses having memory cells including a monolithic semiconductor channel | Electricity | 3 | Active |
| US11056505B2 | Integrated assemblies having one or more modifying substances distributed within semiconductor material, and methods of forming integrated assemblies | Electricity | 3 | Active |
| US11037956B2 | Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies | Electricity | 2 | Active |
| US11538819B2 | Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells | Electricity | 1 | Active |
| US11672120B2 | Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies | Electricity | 1 | Active |
| US12150303B2 | Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies | Electricity | 0 | Active |
| US12144176B2 | Integrated assemblies having one or more modifying substances distributed within semiconductor material, and methods of forming integrated assemblies | Electricity | 0 | Active |
| US11844202B2 | Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells | Electricity | 0 | Active |
| US12288585B2 | Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells | Electricity | 0 | Active |
| US10790290B2 | 3D NAND with integral drain-end select gate (SGD) | Electricity | 0 | Active |
| US10879259B2 | Methods and apparatuses having memory cells including a monolithic semiconductor channel | Electricity | 0 | Active |
| US12432925B2 | Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies | Physics | 0 | Active |
| US12010850B2 | Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies | Physics | 0 | Active |
| US11744072B2 | Integrated assemblies which include stacked memory decks | Physics | 0 | Active |
| US11107831B2 | Methods of forming integrated assemblies include stacked memory decks | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.