Latent read disturb mitigation in memory devices
US11847335B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 25, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Mar 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.