Parallel computational architecture with reconfigurable core-level and vector-level parallelism
US11847553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2018 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Sep 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Neural network processing hardware using parallel computational architectures with reconfigurable core-level and vector-level parallelism is provided. In various embodiments, a neural network model memory is adapted to store a neural network model comprising a plurality of layers. Each layer has at least one dimension and comprises a plurality of synaptic weights. A plurality of neural cores is provided. Each neural core includes a computation unit and an activation memory. The computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The computation unit has a plurality of vector units. The activation memory is adapted to store the input activations and the output activations. The system is adapted to partition the plurality of cores into a plurality of partitions based on dimensions of the layer and the vector units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.