Patterning semiconductor devices and structures resulting therefrom
US11848209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Jul 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3088
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.