Semiconductor package and manufacturing method thereof
US11848233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2022 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Mar 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0574
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.