Method of fabricating semiconductor structure
US11848353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/699
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a semiconductor layer on a semiconductor substrate. The semiconductor layer is patterned to form a semiconductive structure. Each of widths of two ends of the semiconductive structure is wider than a width of a middle of the semiconductive structure. The semiconductive structure is doped to form a doped semiconductor structure. An isolation structure is formed to surround the doped semiconductor structure. A recessing process is performed such that two trenches are formed on the doped semiconductor structure, and first, second and third portions of an active region are formed on the semiconductor substrate. A first gate structure and a second gate structure are formed in the trenches such that the first portion and the third portion are partially spaced apart by the first gate structure, and the second portion and the third portion are partially spaced apart by the second gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.