Polarization controlled transistor
US11848371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Dec 19, 2023 |
| Priority date | — |
| Expiry date | Nov 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.