Memory device with dynamic cache management
US11853205B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Feb 21, 2023 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Feb 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.