Software-hardware memory management modes
US11853225B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Oct 12, 2020 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Oct 12, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.