Read clock start and stop for synchronous memories
US11854602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jun 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.