Read threshold adjustment techniques for memory
US11854641B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Sep 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.