Performing select gate integrity checks to identify and invalidate defective blocks
US11854644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Feb 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.