Inventor · San Jose, CA, US

Murong Lang

72Patents
3h-index
34Co-inventors
58Inventor score

Filing activity: Mar 7, 2016 → May 14, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9852800B2 Adaptive determination of program parameter using program of erase rate Physics 20 Active
US10790036B1 Adjustment of read and write voltages using a space between threshold voltage distributions Physics 8 Active
US10908845B1 Managing threshold voltage drift based on a temperature-dependent slope of the threshold voltage drift of a memory sub-system Physics 3 Active
US11495316B1 Optimized seasoning trim values based on form factors in memory sub-system manufacturing Physics 2 Active
US11901014B2 Partial block handling in a non-volatile memory device Physics 2 Active
US10726925B2 Manage source line bias to account for non-uniform resistance of memory cell source lines Electricity 2 Active
US11960745B2 Empty page scan operations adjustment Physics 1 Active
US10910069B2 Manage source line bias to account for non-uniform resistance of memory cell source lines Electricity 1 Active
US12014049B2 Adaptive sensing time for memory operations Physics 1 Active
US11244740B1 Adapting an error recovery process in a memory sub-system Physics 1 Active
US11742029B2 Adjusting read-level thresholds based on write-to-write delay Physics 1 Active
US11526295B2 Managing an adjustable write-to-read delay of a memory sub-system Physics 1 Active
US10971228B2 Adaptive application of voltage pulses to stabilize memory cell voltage levels Physics 1 Active
US11854644B2 Performing select gate integrity checks to identify and invalidate defective blocks Physics 1 Active
US11740959B2 Dynamic voltage setting optimization during lifetime of a memory device Physics 1 Active
US11861178B2 Managing a hybrid error recovery process in a memory sub-system Physics 1 Active
US11107543B2 Adjustment of read and write voltages using a space between threshold voltage distributions Physics 0 Active
US11307799B2 Managing threshold voltage drift based on operating characteristics of a memory sub-system Physics 0 Active
US11914889B2 Managing an adjustable write-to-read delay based on cycle counts in a memory sub-system Physics 0 Active
US12026394B2 Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system Physics 0 Active
US11977480B2 Scaling factors for media management operations at a memory device Physics 0 Active
US12051471B2 Read disturb management Physics 0 Active
US11698731B2 Performance throttling based on power-off time Emerging Cross-Sectional Technologies 0 Active
US12050777B2 Adaptive scanning of memory devices with supervised learning Physics 0 Active
US12431215B2 Dynamic read calibration Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.