Semiconductor method and device
US11854901B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2022 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jun 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.