Embedded chip package and manufacturing method thereof
US11854920B2 · kind B2 · utility
0Cited by
0References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2020 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Jan 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/18
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embedded chip package according to an embodiment of the present application may include at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.