Package structure having a plurality of chips attached to a lead frame by redistribution layer
US11854949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Feb 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.