Wafer chip scale packages with visible solder fillets
US11855024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Dec 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.