Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same
US11856765B2 · kind B2 · utility
1Cited by
13References
14Claims
0Family size
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Key dates
| Filing date | May 11, 2021 |
| Grant date | Dec 26, 2023 |
| Priority date | — |
| Expiry date | Mar 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/764
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.