Managing programming convergence associated with memory cells of a memory sub-system
US11862257B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 17, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Nov 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.