Deferred communications over a synchronous interface
US11868300B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 3, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Jun 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.