Memory devices including gate leakage transistors
US11869590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Feb 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.