Scalable high speed high bandwidth IO signaling package architecture and method of making
US11869842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2019 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Apr 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.