Self-aligned gate endcap (SAGE) architectures without fin end gap

US11869889B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Szuya S. Liao · Portland, US
• Scott B. Clendenning · Portland, US
• Jessica M. Torres · Portland, US
• Lukas Baumgartel · Portland, US
• Kiran CHIKKADI · Hillsboro, US
• Diane LANCASTER · Hillsboro, US
• Matthew V. Metz · Portland, US
• Florian Gstrein · Portland, US
• Martin M. Mitan · Beaverton, US
• Rami Hourani · Santa Clara, US

Key dates

• Filing date: Sep 23, 2019
• Grant date: Jan 9, 2024
• Expiry date: Apr 18, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0186
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.