Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process

US11869891B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jun Sung Kang · Hillsboro, US
• Kai Loon Cheong · Beaverton, US
• Erica J. Thompson · Beaverton, US
• Biswajeet Guha · Hillsboro, US
• William Hsu · Hillsboro, US
• Dax M. Crum · Beaverton, US
• Tahir Ghani · Portland, US
• Bruce Beattie · Portland, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: Jan 9, 2024
• Expiry date: Aug 11, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.