High voltage transistor device and method for fabricating the same
US11869953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Sep 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/292
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.