Memory including a plurality of portions and used for reducing program disturbance and program method thereof
US11875862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2023 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Jan 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a first set of word lines in a first zone and a second set of word lines in a second zone. When programming memory cells coupled to a first target word line of the first set of word lines, a first pass voltage may be applied to at least one word line of the first set of word lines. When programming memory cells coupled to a second target word line of the second set of word lines, a second pass voltage may be applied to at least one word line of the second set of word lines. The at least one word line of the first set of word lines and the at least one word line of the second set of word lines have been programmed. The second pass voltage may be higher than the first pass voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.