Microelectronic devices having features with a fin portion of different sidewall slope than a lower portion, and related methods and electronic systems
US11877434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2020 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Feb 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.