Inventor · Boise, ID, US

Alex J. Schrinsky

30Patents
3h-index
41Co-inventors
59Inventor score

Filing activity: Aug 23, 2004 → Jul 9, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US9754946B1 Methods of forming an elevationally extending conductor laterally between a pair of conductive lines Electricity 21 Active
US7491641B2 Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line Electricity 19 Active
US9330934B2 Methods of forming patterns on substrates Electricity 4 Active
US11239242B2 Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies Electricity 3 Active
US7262053B2 Terraced film stack Electricity 3 Expired
US9082714B2 Use of etch process post wordline definition to improve data retention in a flash memory device Electricity 3 Active
US7898019B2 Semiconductor constructions having multiple patterned masking layers over NAND gate stacks Electricity 2 Active
US7118966B2 Methods of forming conductive lines Electricity 2 Expired
US7476588B2 Methods of forming NAND cell units with string gates of various widths Electricity 2 Active
US8309424B2 Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods of forming semiconductor constructions Electricity 2 Active
US8802525B2 Methods of forming charge storage structures including etching diffused regions to form recesses Electricity 2 Active
US7927964B2 Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods of forming semiconductor constructions Electricity 2 Active
US9613864B2 Low capacitance interconnect structures and associated systems and methods Electricity 2 Active
US8367303B2 Semiconductor device fabrication and dry develop process suitable for critical dimension tunability and profile control Electricity 1 Active
US7595521B2 Terraced film stack Electricity 1 Active
US9082721B2 Structures comprising masks comprising carbon Electricity 1 Active
US10347643B1 Methods of forming integrated assemblies having dielectric regions along conductive structures Electricity 1 Active
US9911653B2 Low capacitance interconnect structures and associated systems and methods Electricity 0 Active
US10134741B2 Methods of forming an elevationally extending conductor laterally between a pair of conductive lines Electricity 0 Active
US8409457B2 Methods of forming a photoresist-comprising pattern on a substrate Physics 0 Active
US9087737B2 Methods of forming charge storage structures including etching diffused regions to form recesses Electricity 0 Active
US7468533B2 Terraced film stack Electricity 0 Active
US8696922B2 Methods of plasma etching platinum-comprising materials, methods of processing semiconductor substrates in the fabrication of integrated circuitry, and methods of forming a plurality of memory cells Electricity 0 Active
US11088147B2 Apparatus with doped surfaces, and related methods with in situ doping Electricity 0 Active
US9136331B2 Semiconductor constructions Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.