Memory cell of non-volatile memory
US11877456B2 · kind B2 · utility
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3References
16Claims
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Key dates
| Filing date | Jul 21, 2021 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Mar 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell of a non-volatile memory includes a memory element. The memory element is a transistor. The memory element includes an asymmetric spacer. In the memory element, a channel under the wider part of the spacer is longer. When the program operation of the memory element is performed, more carriers are injected into a charge-trapping layer of the spacer through the longer channel. Consequently, the program operation of the memory element is performed more efficiently, and the time period of performing the program operation is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.