Vertical 3D memory device and accessing method
US11877457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2020 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | May 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.