Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region
US11877520B2 · kind B2 · utility
1Cited by
3References
17Claims
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Key dates
| Filing date | Feb 9, 2023 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Feb 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.