Systems and methods for performing nibble-sized operations on matrix elements
US11886875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2018 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Dec 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to systems and methods for performing nibble-sized operations on matrix elements. In one example, a processor includes fetch circuitry to fetch an instruction, decode circuitry to decode the fetched instruction the fetched instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode to indicate the processor is to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix. The exemplary processor includes execution circuitry to execute the decoded instruction as per the opcode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.