Interconnect structures and methods of fabrication

US11887887B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Manish Chandhok · Beaverton, US
• Ramanan V. Chebiam · Hillsboro, US
• Brennen Mueller · Portland, US
• Colin T. Carver · Hillsboro, US
• Jeffery D. Bielefeld · Forest Grove, US
• Nafees Kabir · Portland, US
• Richard Vreeland · Beaverton, US
• William Brezinski · Beaverton, US

Key dates

• Filing date: Jun 27, 2022
• Grant date: Jan 30, 2024
• Expiry date: Jun 27, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06527
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.