Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns
US11892501B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jul 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC) test engine generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design. A diagnostics engine that receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by an ATE, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern. The diagnostics engine employs a fault simulator to fault-simulate the N-cycle at-speed test patterns against a fault model that includes a first set of transition faults and/or defects and fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.