Concurrent command limiter for a memory system
US11893280B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Aug 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.