Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip
US11893336B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jul 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.