Gate-all-around integrated circuit structures fabricated using alternate etch selective material
US11894368B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Dec 26, 2019 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jun 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.